1. Field of the Invention
The invention relates to a device for baseband processing, and more particularly, to a device for WLAN (Wireless Local Area Network) baseband processing with DC (Direct Current) offset reduction.
2. Description of the Prior Art
In the wireless communication field, a zero-IF receiver (zero intermediate frequency receiver, or zero-IF RF, so-called direct-down conversion radio frequency receiver) is one of the practical choices for implementing a communication system. While receiving an antenna signal, which is a baseband signal representing transmitted data arithmetically multiplied by a carrier of a predetermined frequency, a zero-IF receiver derives the baseband signal from one multiplication of the received signal and the carrier rather than a plurality of multiplications of the received signal and carriers of intermediate frequencies, so that a cost-effective design of lower number of external parts can be achieved. Hence, the zero-IF receivers became popular. Of concern, the zero-IF receiver usually generates unwanted DC (Direct Current) offsets when the gain of an amplifier of a previous system for preprocessing in the zero-IF receiver is changed. Furthermore, during a direct-down conversion process (the baseband signal deriving process of the zero-IF receiver), some quasi-DC offsets (noises of low frequencies, whose spectrum locates near that of the DC offsets) are generated. Most of the zero-IF receivers have a built-in DC reduction function. However, it takes long time to reduce significant amounts of DC offset.
This DC offset reduction duration impacts the receiver performance in some wireless applications, for example, IEEE 802.11 Wireless LAN. Because of its packet transmission architecture, WLAN (Wireless Local Area Network) receivers have limited time to perform the AGC (Auto-Gain Control, that is, gain control training, or gain training), which adjusts the strength of an intermediate analogue signal generated by the previous system to achieve better dynamic range of the intermediate analogue signal for further baseband processing by a baseband processor. The lower the DC offset during the gain training period, the more accurate the gain setting by the baseband processor.
FIG. 1 is a diagram of related signals, waveforms, and time sequences while the zero-IF receiver and the baseband processor are operating. In FIG. 1, from top to bottom, the waveforms drawn with solid-lines represent the DC offset, the baseband signal, the quasi-DC-offset, and the composite signal (the intermediate analogue signal) where the baseband signal, the quasi-DC-offset, and the composite signal are shown with envelopes of the signal sweeps. The pattern inside the envelopes represents the components of each signal parabolically. The horizontal axis denotes the time, and the vertical axis denotes the signal amplitude. A signal packet shown in FIG. 1 starts at t0 and ends at t2 along the time axis. A significant DC offset arises at the beginning of the signal packet (that is, at t0). The interval between t0 and t1 represents the gain training period.
Please refer to FIG. 2 showing a block diagram of a combination of a zero-IF receiver 100 and a baseband processor 200 according to the prior art. The signal connection between the zero-IF receiver 100 and the baseband processor 200 can be either differential or a single-ended connection. For simplicity of comparison between the present invention and the prior art and focusing on the novelty of the present invention, only single-ended connection will be illustrated in the following. The related previous system 102 of the baseband processor 200 is shown in the zero-IF receiver 100. The previous system 102 is coupled to an antenna 104 for preprocessing an antenna signal detected by the antenna 104. The previous system 102 comprises an LNA 106 (Low Noise Amplifier) coupled to the antenna 104 for amplifying the signal detected by the antenna 104 and generating at an output an amplified signal, a mixer 108 coupled to the output of the LNA 106 for mixing the amplified signal with an oscillator signal of a predetermined frequency received from an Osc 110 (Oscillator) and generating at an output a mixed signal, a GA 112 (Gain Amplifier) coupled to the output of the mixer 108 for adjusting the strength of the mixed signal according to a gain control signal received from a gain controller 204 of the baseband processor 200 and generating at an output an adjusted signal, and an LPF 114 (Low Pass Filter) coupled to the output of the GA 112 for filtering the adjusted signal and generating the intermediate analogue signal as the output of the previous system 102 and as the output of the zero-IF receiver 100. The baseband processor 200 comprises an ADC 202 (Analogue-to-Digital Converter) coupled to the output of the previous system 102 for converting the intermediate analogue signal received from the previous system 102 into a digital signal and generating at an output the digital signal, the gain controller 204 coupled to the output of the ADC 202 for estimating a DC (Direct Current) offset of the digital signal and generating at an output the gain control signal, and a demodulator 206 coupled to the output of the ADC 202 for demodulating the digital signal.
As mentioned, the unwanted DC offset introduced into the baseband processor from the previous system 102 will make the ADC 202 saturated. Most baseband processors have a built-in RF gain controller such as the gain controller 204 of FIG. 2 to reduce the gain of an amplifier such as the GA 112 of FIG. 2 when an ADC such as the ADC 202 is saturated, but this does not reduce the DC offset and indeed decreases the dynamic range of the intermediate analogue signal. Most of the zero-IF receivers have a built-in DC reduction function but it takes a long time to reduce significant amounts of DC offset and does not match the requirement of a system having limited process time to perform AGC mentioned above.